Field of the Invention
The invention relates in general to a time and cell de-interleaving circuit and method, and more particularly to a time and cell de-interleaving circuit and method capable of reducing the number of times of accessing a system memory.
Description of the Related Art
In general, before a Digital Video Broadcasting-Second Generation Terrestrial (DVB-T2) broadcast signal is transmitted, cell interleaving and time interleaving processes are performed on data to be transmitted to minimize effects that various types of interference has on transmitted data, so that the receiver may obtain correct transmitted data. After the signal is received at the receiver, time de-interleaving and cell de-interleaving processes are performed on the received signal to correctly decode the data. FIG. 1 shows a block diagram of a conventional signal receiver 100. The signal receiver 100 includes a demodulator 110, a frequency de-interleaving circuit 120, a time de-interleaving circuit 130, a cell de-interleaving circuit 140, a de-mapping circuit 150 and a decoding circuit 160. An input signal is a modulated signal (e.g., a quadrature amplitude modulation (QAM) signal based on orthogonal frequency division multiplexing (OFDM)), and is processed by the demodulator 110 to obtain an interleaved signal that includes information of two orthogonal components (I and Q) and a signal-to-noise ratio (SNR). After de-interleaving processes performed by the frequency de-interleaving circuit 120, the time de-interleaving circuit 130 and the cell de-interleaving circuit 140, the data is rearranged in a correct sequence. The processed data is then computed by de-mapping circuit 150 to restore into bit information, which is next processed (e.g., a low-density parity check (LPDC) and BCH decoding) by the decoding circuit 160 to obtain the transmitted data.
The time de-interleaving operation is performed in a unit of one time interleaving (TI) block. Each TI block includes NFEC forward error correction (FEC) blocks, and each FEC block includes Ncell cells. Assume that one TI block includes four FEC blocks (NFEC=4), and each FEC block includes 40 cells (Ncell=40). When the transmitter performs time interleaving process, the size of a dynamic random access memory (DRAM) is set as Nr rows and Nc columns, where Nr is Ncell/5 (8 in this example) and Nc is NFEC×5 (20 in this example). FIG. 2a and FIG. 2b are configuration diagrams of a memory conventionally used for time interleaving process. The size of the memory is Nr×Nc cells, and the value in each grid represents the sequence of writing/reading into/from (FIG. 2a indicates the writing sequence and FIG. 2b indicates the reading sequence) memory addresses. In this example, the word read/written from/into the memory is equal to the size (e.g., 32 bits) of one cell. In the writing operation in FIG. 2a, the cells are written sequentially and vertically from the upper left corner, and a next column is written after a previous column is fully written. In the reading operation in FIG. 2b, the cells are read sequentially and horizontally from the upper left corner, and a next row is read after a previous row is completely read. Assuming that the sequences for the addresses for writing in FIG. 2a also represent the numbers of the written cells, the number sequence of the written cells is: 0, 1, 2, 3, . . . , 78, 80, . . . , 158, and 159, and the number sequence of the read cells is 0, 8, 16, 24, . . . , 155, 4, . . . , 151 and 159, hence achieving an effect of dispersing the cells.
FIG. 3 shows a block diagram of a time de-interleaving circuit and a cell de-interleaving circuit of a conventional signal receiver. A time de-interleaving circuit 130 includes a DRAM 132, a writing address generator 134 and a reading address generator 136. Through the controls of the writing address generator 134 and the reading address generator 136, the cells of a TI block are sequentially and vertically written from the upper left corner of the DRAM 132, and a next column is written after a previous column is fully written, whereas the cells are sequentially and horizontally read from the upper left corner of the DRAM 132, and a next row is read after a previous row is completely read, hence completing the time de-interleaving process. However, the numbers of columns and rows are respectively equal to the numbers of rows and columns of the transmitter, and so the size of the DRAM 132 is designed to be Nc×Nr (given the DRAM 132 is written according to a horizontal sequence and read according to a vertical sequence, the size of the DRAM 132 is Nr×Nc). FIG. 4a and FIG. 4b show sequences of writing/reading addresses of a memory of a conventional time de-interleaving process when the memory bandwidth is equal to the size of cells. Similarly, the value in each grid represents the sequence of the memory addresses that are written/read (FIG. 4a indicates the sequence of writing and FIG. 4b represents the sequence of reading), and the size of the word written/read into/from the DRAM 132 each time is also equal to the size of one cell. Thus, in the writing operation in FIG. 4a, the cells are written sequentially and vertically from the upper left corner, and a next column is written after a previous column is fully written. In the reading operation in FIG. 4b, the cells are sequentially and horizontally read from the upper left corner, and a next row is read after a previous row of completely read. The sequence of the numbers of the cells received by the DRAM 132 is the sequence of the interleaved signals: 0, 8, 16, 24, . . . , 155, 4, . . . , 151, 159. After writing to the DRAM 132 according to the sequence in FIG. 4a, the arrangement of the numbers of the cells received in the DRAM 132 is the same as the numbers of the reading sequence shown in FIG. 4b. Thus, the sequence of the numbers of the cells read from the DRAM 132 is: 0, 1, 2, 3, . . . , 79, 80, . . . , 158, 159, and the time de-interleaving operation is then complete (the DRAM 132 is written/read by 160+160=320 times). In a unit of FEC blocks (the cells numbered 0˜39 are the 0th FEC block, the cells numbered are the 1st FEC block, and so forth), the cell de-interleaving circuit 140 then performs a cell de-interleaving process according to a permutation rule by using a cell de-interleaving (CDI) buffer 142 (generally implemented by an SRAM).
FIG. 5 shows a schematic diagram of a storage state, a permutation rule and an output sequence of cells of a conventional CDI buffer 142. The table on the left represent storage addresses of the 0th FEC block in the CDI buffer 142, the numbers (3, 7, 11 . . . ) on the right of each row represents memory addresses (the 1st row corresponds to memory addresses 0 to 3, the 2nd row corresponds to memory addresses 4 to 7, . . . ), and the CDI buffer 142 sequentially fills in the received cells according to an increasing order of the memory addresses. The table in the middle shows a schematic diagram of a permutation rule of the cell de-interleaving process, the numbers represent read addresses, which are sequentially and horizontally read from the upper left corner, and a next row is read after a previous row is completely read. Thus, the reading sequence of the memory addresses is address 0, address 32, address 1, . . . , address 10, address 37, address 2, . . . , and address 34. As the storage addresses of the cells are identical to the cell numbers, the output sequence of the CDI register 142 is, 0, 32, 1, . . . , and 34 (as shown by the table on the right), thus completing the cell de-interleaving process.
In response to the design trend of system-on-chip (SoC), the DRAM 132 used by the time de-interleaving circuit 130 needs to be shared with other circuits in the system. However, due to a limited bandwidth of the DRAM 132, each circuit needs to minimize the number of times of accessing the DRAM 132 in order not to drag the performance of the system. One method for reducing the number of times of accessing the DRAM 132 is to increase the bandwidth in a way that the word read/written each time is increased. Assuming that the bandwidth of the DRAM 132 multiplied by four times (the word becomes 128 bits, and four cells are read/written each time), although the configuration of the memory is unchanged, the sequences of the addresses read/written are changed. FIG. 6a and FIG. 6b show schematic diagrams of storage addresses and reading/writing sequences of cells in a memory in a conventional time de-interleaving process and when a memory bandwidth is four times the size of cells. The vertical values (0˜159) represent the numbers of the cells, and the horizontal values (0˜39 in FIG. 6a, and 0˜159 in FIG. 6b) represent the writing/reading sequences. FIG. 6a depicts the sequences of writing to the DRAM 132. During a writing operation, the words are sequentially and vertically written from the upper left corner. The words of the cells numbered 0, 8, 16 and 24 are written in the 0th writing operation, the words of the cells numbered 32, 40, 48 and 56 are written in the 1st writing operation, and so forth. Thus, a total of 40 writing operations need be performed for the 160 cells in the DRAM 132. FIG. 6b depicts the sequences of reading from the DRAM 132. During a reading operation, the words are sequentially and horizontally read from the upper left corner, with however the cells being read according to a sequence of the cells numbered 0, 1, 2, 3 . . . . That is, the words of the cells numbered 0, 8, 16 and 24 are read in the 0th reading operation, but only the cell numbered 0 is used. The words of the cells numbered 1, 9, 17 and 25 are read in the 1st reading operation, but only the cell numbered 1 is used, and so forth. Thus, in a writing operation, each word is read four times, and a total of 160 reading operations need to be performed for the 40 words. Using the above method for time de-interleaving the 160 cells, the total number of times of writing/reading into/from the DRAM 132 is 40+160=200 times. FIG. 7a and FIG. 7b show other schematic diagrams of storage addresses and reading/writing sequences of cells in a memory in a conventional time de-interleaving operation and when a memory bandwidth is four times the size of cells. FIG. 7a depicts the sequences of writing into the DRAM 132. In this method, although data of four cells is transmitted to the DRAM 132 each time, only one cell is written. That is, the word including the cells numbered 0, 8, 16 and 24 is written in four separate times (corresponding to 0th, 1st, 2nd and 3rd writing operations), and the word of the cells numbered 32, 40, 48 and 56 is written in four separate times (corresponding to the 4th, 5th, 6th and 7th writing operations), and so forth. Thus, the 40 words are written in 160 times. FIG. 7b depicts the sequences of reading from the DRAM 132. The reading operation is performed according to the sequences of the numbers of the cells, and so the word including the cells numbered 0, 1, 2 and 3 is read in the 0th reading operation, the word including the cells numbered 4, 5, 6 and 7 is read in the 1st reading operation, and so forth. Thus, 40 reading operations need to be performed for these 160 cells. Using this method for time de-interleaving, the total number of times of writing/reading into/from the DRAM 132 is 160+40=200 times.
Although increasing the bandwidth of the DRAM (the methods in FIGS. 6a/6b and FIGS. 7a/7b) reduces the number of times of writing into or reading from the DRAM 132, for a system having a high memory utilization frequency, the overall performance of the system may be further enhanced if the number of times of reading/writing the memory during time de-interleaving operations can be reduced.